A behavioral model for the non-linear on-resistance in sample-and-hold analog switches

摘要

This paper presents a behavioral model of the non-linear on-resistance in S&H analog switches. The model is suitable for analysis and design of low-voltage sampled data systems. Simulated results using the ATMEL 0.24μm CMOS process are shown to validate the model. The Advanced-Compact-Mosfet model (ACM), a symmetric drain-to-source model, valid in the whole inversion level regime of MOS transistors, is used as reference.