Silicon Carbide (SiC) gate oxide reliability still remains a crucial issue and is amongst the important consideration factors when it comes to the implementation of SiC MOS-based devices within industrial power electronic applications. Recent studies have emerged assessing the gate oxide reliability of SiC MOSFETs. Such studies are needed in order to fully understand the properties of SiC/SiO2 interface which is currently holding back the industry from fully utilising the superior features that SiC may offer. This paper aims to present experimental results showing the threshold voltage (VTH) and gate leakage current (IGSS) behaviour of SiC MOSFETs when subjected to pulsed-gate switching bias and drain-source bias stress at high temperature over time. The results obtained are then used to investigate the gate-oxide reliability of SiC MOSFETs. 2D TCAD static simulation results showing electric field distribution near the SiC/SiO2 interface are also presented in this paper.
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