On-chip Impedance Transformations for a Standard CMOS Process

摘要

On-chip impedance matching has become a major focus as companies and institutions move closer to a complete System on a Chip (SoC). With limited design area, it is important to obtain maximum power transfer to the required load. This research presents commonly used impedance matching techniques and extends them to include on-chip networks. These networks have inherent problems caused by the common substrate. It will be shown that the resulting parasitics can be calculated to allow analysis and manipulation of the overall design. It will also be demonstrated that the use of on-chip inductors will cause severe mismatch and loss due to their low quality factors. Finally, test networks will be fabricated in a 1.5-micron process to show the validity of the concepts presented.