Algoritmo de estimação de movimento e sua arquitetura de hardware para HEVC

摘要

Video coding has been used in applications like video surveillance, videoconferencing, video streaming, video broadcasting and video storage. In atypical video coding standard, many algorithms are combined to compress avideo. However, one of those algorithms, the motion estimation is the mostcomplex task. Hence, it is necessary to implement this task in real time byusing appropriate VLSI architectures. This thesis proposes a new fast motionestimation algorithm and its implementation in real time. The results show thatthe proposed algorithm and its motion estimation hardware architecture outperforms the state of the art. The proposed architecture operates at amaximum operating frequency of 241.6 MHz and is able to process1080p@60Hz with all possible variables block sizes specified in HEVCstandard as well as with motion vector search range of up to ±64 pixels.