Desenvolvimento de uma arquitetura em hardware prototipada em FPGA para aplicações genéricas utilizando redes neurais artificiais embarcadas

摘要

This work proposes hardware architecture, VHDL described, developed to embeddedArtificial Neural Network (ANN), Multilayer Perceptron (MLP). The present workidealizes that, in this architecture, ANN applications could easily embed severaldifferent topologies of MLP network industrial field. The MLP topology in which thearchitecture can be configured is defined by a simple and specifically data input(instructions) that determines the layers and Perceptron quantity of the network. In orderto set several MLP topologies, many components (datapath) and a controller weredeveloped to execute these instructions. Thus, an user defines a group of previouslyknown instructions which determine ANN characteristics. The system will guaranteethe MLP execution through the neural processors (Perceptrons), the components ofdatapath and the controller that were developed. In other way, the biases and theweights must be static, the ANN that will be embedded must had been trainedpreviously, in off-line way. The knowledge of system internal characteristics and theVHDL language by the user are not needed. The reconfigurable FPGA device was usedto implement, simulate and test all the system, allowing application in several real dailyproblems