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Enhanced Drain Current of 4H-SiC MOSFETs by Adopting a Three-Dimensional Gate Structure

机译:采用三维栅极结构增强4H-SiC MOSFET的漏极电流

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摘要

4H-SiC (0001) metal-oxide-semiconductor field-effect transistors (MOSFETs) with a 3-D gate structure, which has a top channel on the (0001) face and side-wall channels on the {112macr0} face, have been fabricated. The 3-D gate structures with a 1-5-mum width and a 0.8- mum height have been formed by reactive ion etching, and the gate oxide has been deposited by plasma-enhanced chemical vapor deposition and then annealed in N2O ambient at 1300degC. The fabricated MOSFETs have exhibited good characteristics: The I ON/I OFF ratio, the subthreshold swing, and V TH are 109, 210 mV/decade, and 3.5 V, respectively. The drain current normalized by the gate width is increasing with decreasing the gate width. The normalized drain current of a 1-mum-wide MOSFET is 16 times higher than that of a conventional planar MOSFET.
机译:具有3D栅极结构的4H-SiC(0001)金属氧化物半导体场效应晶体管(MOSFET)具有在(0001)面上的顶部沟道和在{112macr0}面上的侧壁沟道被捏造。通过反应离子刻蚀形成了宽度为1-5-5和高度为0.8-m的3-D栅极结构,并且已经通过等离子体增强化学气相沉积法沉积了栅极氧化物,然后在1300°C的N2O环境中进行退火。 。制成的MOSFET具有良好的特性:I ON / I OFF比率,亚阈值摆幅和V TH分别为109、210 mV /十倍和3.5V。通过栅极宽度归一化的漏极电流随着栅极宽度的减小而增加。 1微米宽MOSFET的归一化漏极电流比传统平面MOSFET高16倍。

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