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Digital tracking loops for a programmable digital modem

机译:可编程数字调制解调器的数字跟踪环

摘要

In this paper, an analysis and hardware emulation of the tracking loops for a very flexible programmable digital modem (PDM) will be presented. The modem is capable of being programmed for 2, 4, 8, 16-PSK, 16-QAM, MSK, and Offset-QPSK modulation schemes over a range of data rates from 2.34 to 300 Mbps with programmable spectral occupancy from 1.2 to 1.8 times the symbol rate; these operational parameters are executable in burst or continuous mode. All of the critical processing in both the modulator and demodulator is done at baseband with very high-speed digital hardware and memory. Quadrature analog front-ends are used for translation between baseband and the IF center frequency. The modulator is based on a table lookup approach, where precomputed samples are stored in memory and clocked out according to the incoming data pattern. The sample values are predistorted to counteract the effects of the other filtering functions in the link as well as any transmission impairments. The demodulator architecture was adapted from a joint estimator-detector (JED) mathematical analysis. Its structure is applicable to most signalling formats that can be represented in a two-dimensional space. The JED realization uses interdependent, mutually aiding tracking loops with post-detection data feedback. To expedite and provide for more reliable synchronization, initial estimates for these loops are computed in a parallel acquisition processor. The cornerstone of the demodulator realization is the pre-averager received data filter which allows operation over a broad range of data rates without any hardware changes and greatly simplifies the implementation complexity. The emulation results confirmed tracking loop operation over the entire range of operational parameters listed above, as well as the capability of achieving and maintaining synchronization at BER's in excess of 10(exp -1). The emulation results also showed very close agreement with the tracking loop analysis, and validated the resolution apportionment of the various hardware elements in the tracking loops.
机译:在本文中,将介绍非常灵活的可编程数字调制解调器(PDM)的跟踪环路的分析和硬件仿真。调制解调器能够在2.34至300 Mbps的数据速率范围内针对2、4、8、16-PSK,16-QAM,MSK和Offset-QPSK调制方案进行编程,可编程频谱占用率是1.2至1.8倍符号率;这些操作参数可以突发或连续模式执行。调制器和解调器中的所有关键处理都是在基带上使用非常高速的数字硬件和存储器来完成的。正交模拟前端用于基带和IF中心频率之间的转换。调制器基于表查找方法,其中预先计算的样本存储在内存中,并根据输入的数据模式逐出时钟。样本值经过预失真以抵消链路中其他滤波功能的影响以及任何传输障碍。解调器架构是根据联合估计器(JED)的数学分析改编而来的。其结构适用于可以在二维空间中表示的大多数信令格式。 JED实现使用相互依赖的,相互辅助的跟踪循环以及检测后的数据反馈。为了加快并提供更可靠的同步,在并行采集处理器中计算了这些循环的初始估计。解调器实现的基础是预平均器接收的数据滤波器,该滤波器允许在广泛的数据速率下进行操作而无需任何硬件更改,并大大简化了实现复杂性。仿真结果证实了在上面列出的整个工作参数范围内的跟踪环路操作,以及在超过10(exp -1)的BER时实现并保持同步的能力。仿真结果还显示与跟踪循环分析非常吻合,并验证了跟踪循环中各种硬件元素的分辨率分配。

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  • 作者

    Poklemba John J.;

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  • 年度 1992
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  • 原文格式 PDF
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