Pipelined and trainable architectures for multi-layer neural networks.

摘要

Multi-layer neural networks have a great learning ability and important applications. Hardware implementation of these networks are needed to exploit their full potential. In this thesis, various VLSI architectures for multi-layer neural networks are introduced. These architectures apply a hybrid digital/analog design methodology. The first architecture utilizes external digital weight memory and is trained with the aid of a host computer. The presented building blocks for this architecture are general. They are designed and implemented in a standard 1.2$mu$ CMOS technology. Furthermore, two new general low cost pipelined architectures are introduced. They are independent of the internal architecture of each stage. The additional controller associated with the pipelined schemes are designed and shown to be quite simple. A new neuron with embedded latch is also introduced for one of these architectures. Finally, Madaline rule III has been applied to develop a trainable multi-layer neural network architecture. All the operations for the weight adaptation are performed by the architecture.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses u26 Major Papers - Basement, West Bldg. / Call Number: Thesis1993 .Y394. Source: Masters Abstracts International, Volume: 32-02, page: 0694. Co-Advisers: M. Ahmadi; M. Shridhar. Thesis (M.A.Sc.)--University of Windsor (Canada), 1993.