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A 2-digit multidimensional logarithmic number system filterbank processor for a digital hearing aid.

机译:用于数字助听器的2位多维对数数字系统滤波器组处理器。

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摘要

This thesis addresses the design, implementation, and evaluation of a filterbank for digital hearing aids using a Multidimensional Logarithmic Number System (MDLNS). Hearing loss is a function of both frequency and input level. In a typical digital hearing instrument, the hearing loss compensation is performed by separating the incoming sound into several frequency bands which are then compressed to allow the amplification of low level signals while maintaining the amplitude of high level signals. The demands of low power consumption and small size have led to a number of advances in algorithms, semiconductor technologies and system architectures for completely-in-canal (CIC) hearing aid device. Based on research for digital hearing aids that started in the early 1990u27s, we have developed a new number system (MDLNS) and associated architecture that benefit the digital hearing aid processor in both of these requirements. Although the LNS has been previously considered for digital hearing aid processors, this thesis presents an exploration of the MDLNS for digital hearing aid circuitry. As with the LNS, the MDLNS provides a reduction in the size of the number representation, but the MDLNS promises a lower cost (area.power) implementation of the arithmetic operations required in both the linear and non-linear domains of filtering and compression. In this thesis we discuss an application of the MDLNS on the construction of a finite impulse response FIR filterbank, a major component of digital hearing aid processors. The MDLNS filterbank processor chip was fabricated using a 0.18 micron CMOS technology. After evaluating the MDLNS filterbank and the two state-of-the-art filterbanks using classic binary implementation, we found power, area, and performance of the MDLNS filterbank processor showed competitive results compared to those binary filterbank processors.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses u26 Major Papers - Basement, West Bldg. / Call Number: Thesis2003 .L5. Source: Masters Abstracts International, Volume: 42-02, page: 0647. Adviser: G. A. Jullien. Thesis (M.A.Sc.)--University of Windsor (Canada), 2003.
机译:本文研究了使用多维对数系统(MDLNS)的数字助听器滤波器组的设计,实现和评估。听力损失是频率和输入水平的函数。在典型的数字助听器中,听力损失补偿是通过将进入的声音分成几个频带进行的,然后将其压缩以允许放大低电平信号,同时保持高电平信号的幅度。低功耗和小尺寸的需求已导致用于完全运河(CIC)助听器设备的算法,半导体技术和系统架构取得了许多进步。基于1990年代初开始的对数字助听器的研究,我们开发了一种新的数字系统(MDLNS)和相关的体系结构,在这两个要求中都使数字助听器处理器受益。尽管LNS以前曾被考虑用于数字助听器处理器,但本论文还是对MDLNS用于数字助听器电路的一种探索。与LNS一样,MDLNS减少了数字表示的大小,但是MDLNS承诺可以在滤波和压缩的线性和非线性域中以较低的成本(面积乘以)实现算术运算。在本文中,我们讨论了MDLNS在有限脉冲响应FIR滤波器组(数字助听器处理器的主要组成部分)的构造中的应用。 MDLNS滤波器组处理器芯片是使用0.18微米CMOS技术制造的。在使用经典的二进制实现对MDLNS滤波器组和两个最新的滤波器组进行评估之后,我们发现MDLNS滤波器组处理器的功率,面积和性能与那些二进制滤波器组处理器相比显示出竞争优势。电气和计算机工程系。莱迪图书馆的纸质副本:论文主要论文-西楼地下室。 /电话号码:Thesis2003 .L5。资料来源:国际硕士摘要,第42卷,第0647页。顾问:G。A. Jullien。论文(硕士)-温莎大学(加拿大),2003。

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    Li Hongbo (Jennifer).;

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