0.18 micron CMOS IP core design and methodology.

摘要

When working with 0.18mum or smaller CMOS technologies, current larger technology architectures are not easily scaled and subject to short channel effects. As a result, changes in architecture and/or unconventional transistor sizing must be done. The voltage comparator that has been designed consists of (13) transistors to form the following architectures; a differential input pair, a current mirror and a rail-pulling output stage. Special transistor sizing has been used in the current mirror biasing stage to produce a constant current source for biasing of the input transistors, overcoming the problems of non-constant current and non-constant transconductance due to short channel effects. The performance of the voltage comparator has been verified via software simulations and compared with current state-of-the-art designs. The design has been submitted to the Canadian Microelectronics Corporation for fabrication under the design name ICFWRJSS. The packaged design with bonding pads, occupies an area of 0.26mm2, and is contained in a DIP package. The fabricated chip is expected to arrive at the University in August of 2003. Actual physical testing of the voltage comparator will take place at that time. In addition to the design of the voltage comparator a detailed design methodology has also been developed. The design methodology has been developed in parallel with the comparator design and describes the major steps and considerations taken while designing the voltage comparator. The goal of the design methodology is to provide a robust guide for designing a state-of-the-art system, regardless of the skill level of the designer and regardless of the phase that the designer is at. Source: Masters Abstracts International, Volume: 42-02, page: 0650. Adviser: W. C. Miller. Thesis (M.A.Sc.)--University of Windsor (Canada), 2003.