In this dissertation, architectures, hardware design and prototypes for the realization of 2-D filters are presented. These filtering architectures are capable of attaining real-time processing rates for advanced television systems and are economical in terms of hardware cost, fabrication cost, and power consumption. Sample-and-hold type realizations, operating on 2-D sampled data, based on the standard 2-D discrete-time transfer function H($zsb1,zsb2)$ are presented. Both IIR and FIR realizations are developed in terms of high-speed systolic architectures. The design process culminates in the development of a 2 x 2 recursive prototype. Instead of using the standard discrete-time transfer function it is also possible to develop 2-D filters based on a 2-D hybrid transfer function H(z,s) which involves both z-domain and s-domain variables. These are highly suitable for filtering a raster scanned image, which can be characterized as an input signal X(z,s), which is a function of these same two variables. Design considerations are presented which culminate in the development of a 1 x 1 recursive prototype. The sample-and-hold systolic architecture was employed together with switched-capacitor circuit techniques to develop a 2-D real-time switched-capacitor recursive filter. This type of filter features greater accuracy than a conventional analog circuit as well as advantages for VLSI implementation. In addition to presenting novel design methodologies for hardware prototypes, a novel function block approach for the SPICE simulation of 2-D modular systems with true 2-D data is provided. This approach will serve to greatly facilitate 2-D filter development and improve the efficiency of the design cycle.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses u26 Major Papers - Basement, West Bldg. / Call Number: Thesis1993 .K389. Source: Dissertation Abstracts International, Volume: 56-01, Section: B, page: 0423. Adviser: M. A. Sid-Ahmed. Thesis (Ph.D.)--University of Windsor (Canada), 1994.
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机译：本文提出了实现二维滤波器的体系结构，硬件设计和原型。这些滤波架构能够获得高级电视系统的实时处理速率，并且在硬件成本，制造成本和功耗方面都很经济。提出了基于标准二维离散时间传递函数H（$ z sb1，z sb2）$对二维采样数据进行操作的采样保持类型实现。 IIR和FIR实现都是根据高速脉动体系结构开发的。设计过程最终导致2 x 2递归原型的开发。代替使用标准的离散时间传递函数，还可以基于涉及z域和s域变量的2-D混合传递函数H（z，s）开发2-D滤波器。这些非常适合于过滤光栅扫描图像，该图像可以表征为输入信号X（z，s），这是这两个变量的函数。提出了设计注意事项，最终导致了1 x 1递归原型的开发。采样保持脉动体系结构与开关电容器电路技术一起用于开发2D实时开关电容器递归滤波器。这种类型的滤波器比传统的模拟电路具有更高的精度，并且具有实现VLSI的优势。除了介绍用于硬件原型的新颖设计方法外，还提供了一种新颖的功能块方法，用于具有真实2-D数据的2-D模块化系统的SPICE仿真。这种方法将极大地促进二维滤波器的开发并提高设计周期的效率。电气和计算机工程系。莱迪图书馆的纸质副本：论文主要论文-西楼地下室。 /电话号码：Thesis1993 .K389。资料来源：国际学位论文摘要，第56-01卷，第B部分，第0423页。顾问：M。A. Sid-Ahmed。论文（博士学位）-温莎大学（加拿大），1994。
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