The emphasis in VLSI design has shifted from high speed to low power due to the proliferation of portable electronic systems. Many of the techniques have already been used in low power design with additional techniques emerging continuously at all levels. The goal of this work is to provide a comprehensive study of low-power circuit and design techniques using complementary metal-oxide-semiconductor (CMOS) technology. This will encompass aspects such as circuit design; transistor size, layout technique, cell topology, and circuit design for low power operation while paying particularly attention on the methodology of logic style. This thesis specifically deals with the comparison between static CMOS and complementary pass-transistor logic (CPL) styles, in a 0.35 mum CMOS technology, to determine the most efficient choice for low power design. The comparison study allows a selection procedure between static CMOS and CPL for low-power logic circuits, and provides a set of comparison results for use with other circuit design techniques.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses u26 Major Papers - Basement, West Bldg. / Call Number: Thesis2001 .C66. Source: Masters Abstracts International, Volume: 41-04, page: 1150. Adviser: Graham Jullien. Thesis (M.A.Sc.)--University of Windsor (Canada), 2002.
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