MSE-OFDM is a new multi carrier system, in which one cyclic prefix used for multiple OFDM symbols. The original motivation for the MSE-OFDM proposal is to reduce the redundancy caused by the cyclic prefix. In this paper the design implementation of MSE-OFDM transmitter on a field programmable gate array has been presented. The implementation is made on FPGA since it allows flexibility in design and also it can achieve higher computing speed than digital signal processors . IDFT block in MSE-OFDM transmitter is implemented by IFFT to enhance the speed. This architecture uses radix-2 algorithm for 8 point IFFT and radix-4 algorithm for 16- point IFFT. Here advantage is that IFFT algorithms use only adders, subtractors and shifter only thus minimizing the hardware requirement compared to other architectures. Here implementation of ‘binary source using pseudo random binary generator’ and ‘M-QAM’ has also been presented. Here the signed numbers are represented using 12-bit signed binary 6.6 fixed point representation so that to get more accurate results even for decimal values. The The proposed design is mapped on to Xilinx virtex-5 xc5vlx30-2ff676 based device. XST synthesis tool has been used to synthesize the model. The result shows that maximum frequency of operation is in range of 600- 700 MHz . the system design is optimized in terms of speed,power and area.
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