The reduction of the channel length due to scaling increases the leakage current resulting in a major contribution to the static power dissipation and for stability of the SRAM cell good noise margin is required so noise margin is the most important parameter for memory design. The higher noise margin of the cell confirms the high-speed of SRAM cell. In this work, a novel SRAM cell with eight transistors is being proposed to reduce the static hence total power dissipation. When compared to the conventional 6T SRAM and NC-SRAM cell, the proposed SRAM shows a significant reduction in the gate leakage current, static and total power dissipation while produce higher stability. In the technique employed for the proposed SRAM cell, the operating voltage is reduced in idle mode. The technique led a reduction of 31.2% in the total power dissipation, a reduction of 40.4% on static power dissipation, and The SVNM SINM WTV and WTI of proposed SRAM cell was also improved by 11.17%, 52.30%, 2.15%, 59.1% respectively as compare to 6T SRAM cell and as compare to NC-SRAM cell is 27.26%, 47.44%, 4.31%, 64.44% respectively. It can be found that the proposed cell is taking 28.6% extra area from the conventional SRAM cell whereas it is almost same with NC-SRAM cell. Cadence Virtuoso tools are used for simulation with 90- nm CMOS process technology.
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