Gordon Moore mentioned an exact objective fact in the 1960's that the quantity of gadgets on a chip duplicates like clockwork. The "Moore's Law" is a concise depiction of the persevering intermittent increment in the level of scaling down. Every time the base line width is lessened, we say that another innovation era or innovation hub is presented. Cases of innovation eras are 0.18µm, 0.13µm, 90nm, 65nm, 45nm… eras. The numbers allude to the base metal line width. Poly-Si door length may be littler. At each new hub, the different element sizes of circuit format, for example, the measure of contact openings, are 70% of the past hub. This routine of occasional size lessening is called scaling. Generally, another innovation hub is presented at regular intervals or somewhere in the vicinity I have simulated various electronic circuits using CMOS in MATLAB, P-Spice, multi-sim (ICs used BS170, ZVP4424A) and Nano-CMOS using T-Spice where we can vary the physical dimensions of the MOSFET. The outputs were observed and the time delay was calculated. The above results showed that, as we go on reducing the size, the performance enhances
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