A phase shifter with polar output has been implemented with techniques commonly used for quadrature phase shifters. The hybrid approach employs dual-path programmable gain amplifiers and polyphase filters as cascaded quadrature phase shifter stages. Each stage is implemented using active components as well as differential RC filters which consume less area than the typical LC low-pass/high-pass approach. 5-bit phase resolution has been implemented. A 4-bit linear PGA follows the phase shifter chain for antenna tapering. The RFIC employing LNA and balancing devices has been been designed in a 0.25 _m SiGe BiCMOS technology which guarantees a low cost solution for medium scale integration such as in phased arrays. According to simulation results, a very homogeneous distribution of phase/gain states can be expected over a wide bandwidth. Achieved gain and noise figure in the band of interest (2.9 GHz ... 3.1 GHz) exhibit 25.9 dB and 11.6 dB, respectively, with a power consumption of 114mW.
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