Efficiency and flexibility trade-offs for soft input soft output sphere decoding architectures

摘要

In the past decades, improved algorithms and more densely integrated circuits enabled rapid progress in the area of mobile communications. The fast proliferation of mobile multimedia content and the exponentially increasing data rates demand for more and more efficient wireless transmission principles and receivers. An approach called "MIMO" (multiple input, multiple output) improves the spectral efficiency by transmitting multiple data streams concurrently within the same bandwidth by using multiple transmit and receive antennas. This approach is already part of several mobile communication standards such as LTE, WLAN and HSPA. Aside from an increasing efficiency, mobile receivers need to support a rapidly growing number of communication standards as well as updates after fabrication. Therefore, the trend towards flexibility is also relevant for physical layer receiver architectures. However, flexibility causes costs (e.g. in terms of chip area or energy consumption) which can be orders of magnitude higher than for application specific integrated circuits. In the context of this thesis, efficiency and flexibility aspects have been investigated for "Sphere-Decoding" (SD), an important class of MIMO receiver algorithms. By iterative feedback of bitwise reliability information ("soft-input soft-output", SISO) between the MIMO demodulator and the channel decoder, a spectral efficiency near the theoretical limits can be achieved. The algorithmic basis for SISO SD is well known for some time. However, due to the high complexity of SISO SD, up to the beginning of this work only architectures existed which support the non-iterative soft-output SD. The first SISO SD architecture has been developed in the context of this thesis. It provides a high efficiency with a limited flexibility which allows switching antenna and modulation configurations at runtime. Beyond this architecture, SISO SD implementations for representative programmable architectures have been investigated. The resulting analysis provides an important insight into the trade-offs between efficiency, flexibility and portability of this class of algorithms. Such iterative demodulation/decoding architectures cannot be compared by single points of operations due to their inherent trade-off between complexity and spectral efficiency. Therefore, a special analysis approach has been elaborated as part of this work which enables comparisons under preferably identical scenarios (error rates, throughput latency and chip area). This approach enables reasonable and fair comparisons of complexity, efficiency and flexibility of very different architectures. Based on these analyses, points of operation can be estimated which allow an economic use of SISO-SD architectures in future mobile receivers.