Deep submicron full-custom VLSI design of highly optimized high throughput low latency LDPC decoders

摘要

To satisfy the increasing demand for communication bandwidth more and more complex transmission systems are required. Channel coding as one fundamental block of such systems allows for a receiver-sided detection and correction of communication errors by introducing redundancy. Thereby, Low-Density Parity-Check (LDPC) codes achieve very low bit-error rates which are significantly lower than those of, for example, Turbo codes. Although, LDPC codes have already been introduced by R. G. Gallager in 1962, the complexity of LDPC decoders impeded their monolithic integration for a long time. The progress in VLSI-CMOS technology and the possibility to integrate digital circuits with millions of transistors allowed such an integration only in the recent years. Since then, LDPC codes have been adopted in various communication-system standards. Due to the complexity of the decoding algorithm, LDPC decoders highly impact the system features such as silicon area, throughput, latency, and energy requirements. Therefore, this thesis deals with the conception and design of area-, latency-, and energy-optimized LDPC decoders. For a systematic analysis of different decoder realizations, a new methodology has been developed which has a specified application as the starting point and derives efficient solutions. Therein, the optimization comprises all levels of CMOS design starting from the algorithmic system level and ending with the physical implementation level. As a first step, accurate area, timing, and energy cost models have been derived for two basic decoder architectures to allow for a quantitative analysis and optimizations on various design levels. In the following optimization, these models can be used to quantitatively compare different design strategies. For an analysis of possible fixed-point implementations of the algorithm, a parameterized HDL model has been developed. Based on this model, saturation and quantization effects on the decoding performance have been studied using hardware-accelerated simulations. A systematic analysis of the architecture design space results in a new area-, latency-, and energy-efficient architecture. To verify the efficiency of this new architecture, a LDPC decoder has been designed for an exemplary high-throughput application in a 40-nm CMOS technology. The features of this decoder are compared to the implementations known from literature. It could be shown that the joint optimization on all design levels enables a significant increase of the decoder efficiency in terms of area, throughout and energy by a factor of ten.