As an independent double-gate, silicon-on-insulator transistor, the FlexfetTM is suited for a wide range of applications in analog and digital circuitry. This study investigates the ability of the JFET bottom-gate to adjust and control several parameters in the FlexfetTM as well as shield against performance degradation due to substrate biasing. The device parameters under investigation include drive current, leakage current, and threshold voltage. The newly assigned F-factor describes the ability of FlexfetTM’s bottomgate to adjust the threshold voltage. FlexfetTM exhibits nearly a 10x and 3.5x increase in drive current for the nMOS and pMOS devices, respectively, with a 1 V bottom-gate voltage swing. Comparing the nominal devices with the low-power devices, both the nMOS and pMOS unexpectedly demonstrated higher leakage current for the low-power biasing. F-factors of 0.53 V/V and 0.38 V/V were calculated for the nMOS and pMOS devices, respectively. With a 40 V swing on the substrate potential, the nMOS device showed less than 12 pA increase in leakage current and no more than 20 mV of unwanted Vt shift. The pMOS measured less than 2 pA increase in leakage current and 10 mV of Vt shift for the same substrate biases.
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机译：作为独立的双栅极绝缘体上硅晶体管，FlexfetTM适用于模拟和数字电路的各种应用。这项研究调查了JFET底栅在FlexfetTM中调整和控制多个参数以及屏蔽因衬底偏置而导致的性能下降的能力。研究中的设备参数包括驱动电流，泄漏电流和阈值电压。新分配的F因子描述了FlexfetTM底门调节阈值电压的能力。 FlexfetTM的底栅电压摆幅为1 V，nMOS和pMOS器件的驱动电流分别增加了近10倍和3.5倍。将标称器件与低功耗器件进行比较，nMOS和pMOS都出乎意料地表现出了针对低功耗偏置的更高泄漏电流。对于nMOS和pMOS器件，分别计算出0.53 V / V和0.38 V / V的F因子。在衬底电势上摆幅为40 V的情况下，nMOS器件的漏电流增加不到12 pA，不想要的Vt漂移不超过20 mV。对于相同的衬底偏置，测得的pMOS的漏电流增加小于2 pA，Vt漂移为10 mV。
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