The main memory subsystem has become inefficient. The performance gained has come at the expenses of power consumption, capacity, and cost. This dissertation proposes novel module, DRAM, and interconnect architectures in an attempt to alleviate these trends. The proposed architectures utilize low-cost interconnects and packaging innovations to substantially reduce the power, and increase the capacity and bandwidth of the main memory system.This dissertation develops the theory behind a low-cost packaging technology to create an 8-die and 32-die memory module. The 32-die memory module measures less than 2 cm3.This dissertation also proposes a 4 Gb DRAM architecture utilizing 64 data pins to supplement the memory module design. This DRAM architecture is inline with ITRS roadmaps and consumes 50% less power while increasing bandwidth by 100%. The large number of data pins is made possible with the use of a low power capacitive-coupled interconnect.As part of the capacitive-coupled interconnect, this dissertation proposes a receiver circuit designed for the capacitive interface. The designs were fabricated in 0.5 μm and 65 nm CMOS technologies. The 0.5 μm design operated at 200 Mbps, and consumed less than 3 pJ/bit of energy. While the 65 nm design operated at 4 Gbps, and consumed less than 15 fJ/bit.
展开▼
