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FPGA Implementation of an Adaptive Noise Canceller for Robust Speech Enhancement Interfaces

机译:健壮语音增强接口的自适应噪声消除器的FPGA实现

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摘要

This paper describes the design and implementation results of an adaptive Noise Canceller useful for the construction of Robust Speech Enhancement Interfaces. The algorithm being used has very good performance for real time applications. Its main disadvantage is the requirement of calculating several operations of division, having a high computational cost. Besides that, the accuracy of the algorithm is critical in fixed-point representation due to the wide range of the upper and lower bounds of the variables implied in the algorithm. To solve this problem, the accuracy is studied and according to the results obtained a specific word-length has been adopted for each variable. The algorithm has been implemented for Altera and Xilinx FPGAs using high level synthesis tools. The results for a fixed format of 40 bits for all the variables and for a specific word-length for each variable are analyzed and discussed.
机译:本文介绍了适用于构建健壮语音增强接口的自适应噪声消除器的设计和实现结果。所使用的算法在实时应用中具有非常好的性能。它的主要缺点是需要计算多个除法运算,具有很高的计算成本。除此之外,由于算法中隐含的变量的上限和下限范围较大,因此算法的精度在定点表示中至关重要。为了解决这个问题,研究了精度,并根据获得的结果为每个变量采用了特定的字长。该算法已使用高级综合工具为Altera和Xilinx FPGA实施。分析并讨论了所有变量的固定格式(40位)和每个变量的特定字长的结果。

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