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A hardware mechanism to reduce the energy consumption of the register file of in-order architectures

机译:减少顺序架构寄存器文件能耗的硬件机制

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摘要

This paper introduces an efficient hardware approach to reduce the register file energy consumption by turning unused registers into a low power state. Bypassing the register fields of the fetch instruction to the decode stage allows the identification of registers required by the current instruction (instruction predecode) and allows the control logic to turn them back on. They are put into the low-power state after the instruction use. This technique achieves an 85% energy reduction with no performance penalty.
机译:本文介绍了一种有效的硬件方法,可通过将未使用的寄存器变为低功耗状态来减少寄存器文件的能耗。将获取指令的寄存器字段旁路到解码级可以识别当前指令所需的寄存器(指令预解码),并允许控制逻辑将其重新打开。指令使用后,它们进入低功耗状态。该技术实现了85%的能耗降低,而不会降低性能。

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