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Synthesis of Cerium Dioxide High-k Thin Films as a Gate Dielectric in MOS Capacitor

机译:MOS电容器中作为栅极电介质的二氧化铈高k薄膜的合成

摘要

In the present study, the Al/CeO2 / p-Si MOS capacitor was fabricated by depositing the Aluminium (Al) metal layer by thermal evaporation technique on sol-gel derived CeO2 high-k thin films on p-Si substrate. The deposited CeO2 films were characterized by Ellipsometer to study the refractive index that is determined to be 3.62. The FTIR analysis was carried out to obtain chemical bonding characteristics. Capacitance-voltage measurements of Al/CeO2 /p-Si MOS capacitor were carried out to determine the dielectric constant, equivalent oxide thickness (EOT) and flat band shift (VFB) for the deposited CeO2 film of 16.22, 1.62 nm and 0.7 V respectively. The conductance voltage curve was used to determine the interface trap density (Dit) at the CeO2 / p-Si interface that is calculated to be 1.29 × 1013 cm – 2 eV – 1 for measurement frequency of 500 kHz.When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/31926
机译:在本研究中,Al / CeO2 / p-Si MOS电容器是通过在p-Si衬底上的溶胶-凝胶衍生的CeO2高k薄膜上通过热蒸发技术沉积铝(Al)金属层而制成的。用椭偏仪对沉积的CeO2薄膜进行表征,以研究确定为3.62的折射率。进行FTIR分析以获得化学键合特性。进行了Al / CeO2 / p-Si MOS电容器的电容电压测量,以确定沉积的CeO2薄膜的介电常数,等效氧化物厚度(EOT)和平带移(VFB)分别为16.22、1.62 nm和0.7 V 。使用电导电压曲线确定CeO2 / p-Si界面处的界面陷阱密度(Dit),对于500 kHz的测量频率,其计算值为1.29×1013 cm – 2 eV – 1。 ,请使用以下链接http://essuir.sumdu.edu.ua/handle/123456789/31926

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