A “real time” monitoring system which enables to observe internal degradation process to failure of power semiconductors under power cycling test is proposed. The system was realized by combining a scanning acoustic tomography (SAT/SAM), power stress controlling, device cooling, water jet system and chip temperature monitoring. Two contradictory problems, namely, electrically wiring for power cycling and waterproof of device for SAT imaging were compatible with each other by experimental setup with an original water tank. Self-heating of power devices was supressed by controlling temperature of water which is couplant of ultrasonic wave for the SAT. A demonstration of this system was performed by using an IGBT module which maximum rating of collector current was 400 A (DC).
展开▼
