A large-scale, self-consistent thermal simulator for the layout optimization of power III-V field-effect and bipolar transistors

摘要

The paper describes the application of a 3D large-scale thermal simulation tool to the layout analysis and optimization of power III-V devices. A short description is provided of the hybrid algorithm (Green's function and finite-element) exploited by the simulator. The model accounts for non-linear multilayered substrates, heat conduction through surface metallizations and via holes, and substrate thinnings. Case studies are discussed to demonstrate the effectiveness of the approach in investigating the thermal behaviour of different device layouts.