Design Data for Hot-via Interconnects in Chip Scale Packaged MMICs up to 110 GHz

摘要

Theoretical and experimental design data for the modeling of bump- to hot-via interconnect transitions, for use in chip-scale package MMICs, is presented. The theoretical data is based on cascaded analytical transmission line models, derived from rigorous electromagnetic analysis. Excellent agreement has been observed between theory and experiment up to 110 GHz. This modeling approach is validated with the characterization of a broadbandudmillimeter-wave PHEMT amplifier MMIC using the hot-via and bump interconnects, for mounting on a carrier substrate; the measurements are as well, in very good concordance with the predicted performance, including the effects of BCB coating, backside metallization and bump- to hot-via transitions.