An integrated 12-GHz static frequency divider with a selectable division ratio (16/1, 64/1) realised in a Silicon Germanium technology dedicated for high volume production, is presented. It operates at low bias voltage (2.7-3.6V) providing balanced output signals on 50-ohm loads. The chosen architecture, the adopted design approach and used technology led to a good trade-off among maximum input frequency, input sensitivity, noise floor, power consumption, division ratioes and die size compared with the current high frequency dividers. The circuit features make itself a versatile block for high frequency PLL systems, while the circuit core can be used as a macrocell for the design of totally integrated fast PLL’s.
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