This paper introduces fully digital implementations of four di erent systems in the 3rd order jerk-equation based chaotic familyudusing the Euler approximation. The digitization approach enables controllable chaotic systems that reliably provide sinusoidal orudchaotic output based on a selection input. New systems are introduced, derived using logical and arithmetic operations betweenudtwo system implementations of different bus widths, with up to 100x higher maximum Lyapunov exponent than the original jerkequationudbased chaotic systems. The resulting chaotic output is shown to pass the NIST sp. 800-22 statistical test suite for pseudorandomudnumber generators without post-processing by only eliminating the statistically defective bits. The systems are designedudin Verilog HDL and experimentally verified on a Xilinx Virtex 4 FPGA for a maximum throughput of 15.59 Gbits/s for the nativeudchaotic output and 8.77 Gbits/s for the resulting pseudo-random number generators.
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