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Développement et caractérisation de procédés de gravure des espaceurs Si3N4 pour les technologies FDSOI

机译:FDSOI技术的Si3N4隔离层蚀刻工艺的开发和表征

摘要

In CMOS technologies on FDSOI substrate, the silicon recess in transistor's source/drain regions caused by multiple etch steps is a critical parameter. The plasma etching of Si3N4 spacers, which occurs after the gate etch step, must allow the fabrication of straight spacer profiles which will define the effective channel length under the gate, while minimizing the consumption of the underlying silicon thin film. Moreover, the silicon surface state generated by the spacers etching must not prevent the epitaxial silicon growth used for the realization of raised source/drain regions.The study of current spacers etch processes based on CHxFy/O2 chemistries shows that silicon is consummated by oxidation when the plasma lands on the silicon surface. Furthermore, the XPS analysis shows that carbon is implanted in the silicon substrate by plasma ions, and that it inhibits the silicon epitaxial regrowth. We are able to reduce the implanted carbon concentration without any additional silicon recess by using non-oxidizing plasma post-treatments based on hydrogen.After identifying the limitations of current etch processes, we developed and characterized Si3N4 spacers etch processes using synchronously pulsed CH3F/O2/He plasmas. The modulation in short pulses with low duty cycles decreases the dose of high energy ions bombarding the substrate, which allows to reduce the oxidized silicon thickness as well as the concentration of implanted carbon. The addition in the plasma of a Si-containing gas, SiCl4 or SiF4, also leads to a reduction of the silicon consumption thanks to the deposition of a SiOxFy layer by radicals from the gas phase. The best result is obtained with a CH3F/O2/He plasmas pulsed at 1 kHz and 10% duty cycle with the addition of 5 or 10 sccm of SiF4 : the silicon recess is then almost zero.We also developed and evaluated an alternative etching technique, based on the implantation of He+ and H+ ions followed by a HF wet etch, for the etching of Si3N4 spacers. This innovative etch process does not generate any silicon recess and shows some promising results.
机译:在FDSOI基板上的CMOS技术中,由多个蚀刻步骤导致的晶体管源/漏区中的硅凹槽是关键参数。在栅极蚀刻步骤之后进行的Si3N4隔离层的等离子刻蚀必须允许制造直的隔离层轮廓,该轮廓将定义栅极下方的有效沟道长度,同时将底层硅薄膜的消耗降至最低。此外,间隔物刻蚀产生的硅表面状态一定不能阻止用于实现升高的源极/漏极区的外延硅生长。基于CHxFy / O2化学物质的当前间隔物刻蚀工艺研究表明,硅在氧化时会被氧化消耗等离子体降落在硅表面上。此外,XPS分析表明碳通过等离子体离子注入到硅衬底中,并且它抑制了硅外延再生。通过使用基于氢的非氧化等离子体后处理,我们能够降低注入的碳浓度而没有任何额外的硅凹陷。在确定了当前蚀刻工艺的局限性之后,我们开发并表征了使用同步脉冲CH3F / O2的Si3N4隔离层蚀刻工艺/他的血浆。具有低占空比的短脉冲调制减少了轰击衬底的高能离子的剂量,从而降低了氧化硅的厚度以及注入的碳的浓度。在等离子体中添加含Si气体(SiCl4或SiF4),由于气相中的自由基沉积了SiOxFy层,因此也导致了硅消耗量的减少。最好的结果是在以1 kHz脉冲和10%占空比的条件下以CH3F / O2 / He等离子体脉冲并添加5或10 sccm的SiF4时:硅凹槽几乎为零。我们还开发并评估了另一种蚀刻技术,基于He +和H +离子的注入,然后进行HF湿法刻蚀,用于刻蚀Si3N4隔离层。这种创新的蚀刻工艺不会产生任何硅凹陷,并且显示出一些可喜的结果。

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    Blanc Romuald;

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  • 年度 2014
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  • 原文格式 PDF
  • 正文语种 fr
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