Caractérisation et modélisation de la fiabilité relative au piégeage dans des transistors décananométriques et des mémoires SRAM en technologie FDSOI

摘要

Nowadays, microelectronic industry is able to manufacture transistors with gate length down to 30nm.At such scales, the variability and reliability issues are a growing concern. Hence, understanding the interplaybetween these two concerns is essential to guarantee good lifetime estimation of the devices. Currently, theBias Temperature Instability (BTI), which is mostly due to the carrier trapping occurring in the gate oxide,appears to be the principal source of degradation responsible for the ageing of transistor device. Thismanuscript presents a complete study of the BTI degradation occurring on small and big transistors and onStatic Random Access Memory (SRAM) cells. Thus, as a first step, several electrical characterization techniquesto evaluate the BTI degradation are presented. The necessity of fast measurement in order to avoid most of therelaxation effect occurring after the BTI stress is emphasized. Then, using these fast measurement techniques,a complete study of the Negative BTI (NBTI) on large devices is presented. Then, the manuscript focuses on thesmall devices: transistors and memory cells. First, a modeling of the trapping mechanism in the gate oxide ofsmall transistor is presented. In particular, 3D electrostatic simulations allowed us to understand the particularinfluence of the traps over the threshold voltage (VT) of the small transistors. Finally, the case of the SRAM isstudied. Finally, the impact of the degradation occurring at transistor level and impacting the functioning of theSRAM bitcells is investigated.