Conception, fabrication, caractérisation et modélisation de transistors MOSFET haute tension en technologie avancée SOI (Silicon-On-Insulator)

摘要

Nowadays the scaling of bulk silicon CMOS technologies is reaching physical limits. In this context, the FDSOI technology (fully depleted silicon-on-insulator) becomes an alternative for the industry because of its superior performances. The use of an ultra-thin SOI substrate provides an improvement of the MOSFETs behaviour and guarantees their electrostatic integrity for devices of 28nm and below. The development of high-voltage applications such DC/DC converters, voltage regulators and power amplifiers become necessary to integrate new functionalities in the technology. However, the standard devices are not designed to handle such high voltages. To overcome this limitation, this work is focused on the design of a high voltage MOSFET in FDSOI. Through simulations and electrical characterizations, we are exploring several solutions such as the hybridization of the SOI substrate (local opening of the buried oxide) or the implementation in the silicon film. An innovative architecture on SOI, the Dual Ground Plane EDMOS, is proposed, characterized and modelled. It relies on the biasing of a dedicated ground plane introduced below the device to offer promising RON.S/BV trade-off for the targeted applications.