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DLTS analysis of amphoteric interface defects in high-TiO2 MOS structures prepared by sol-gel spin-coating

机译:溶胶-凝胶旋涂法制备高TiO2 MOS结构两性界面缺陷的DLTS分析

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摘要

High-kappa TiO2 thin films have been fabricated from a facile, combined sol-gel spin - coating technique on p and n type silicon substrate. XRD and Raman studies headed the existence of anatase phase of TiO2 with a small grain size of 18 nm. The refractive index `n' quantified from ellipsometry is 2.41. AFM studies suggest a high quality, pore free films with a fairly small surface roughness of 6 angstrom. The presence of Ti in its tetravalent state is confirmed by XPS analysis. The defect parameters observed at the interface of Si/TiO2 were studied by capacitance - voltage (C - V) and deep level transient spectroscopy (DLTS). The flat - band voltage (V-FB) and the density of slow interface states estimated are -0.9, -0.44 V and 5.24x10(10), 1.03x10(11) cm(-2); for the NMOS and PMOS capacitors, respectively. The activation energies, interface state densities and capture cross -sections measured by DLTS are E-V + 0.30, E-C - 0.21 eV; 8.73x10(11), 6.41x10(11) eV(-1) cm(-2) and 5.8x10(-23), 8.11x10(-23) cm(2) for the NMOS and PMOS structures, respectively. A low value of interface state density in both P-and N-MOS structures makes it a suitable alternate dielectric layer for CMOS applications. And also very low value of capture cross section for both the carriers due to the amphoteric nature of defect indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent. (C) 2015 Author(s).
机译:高κTiO2薄膜是通过在p型和n型硅衬底上采用便捷的组合溶胶-凝胶旋涂技术制成的。 XRD和拉曼研究表明,TiO2的锐钛矿相存在,其晶粒尺寸为18 nm。由椭圆偏振法定量的折射率“ n”为2.41。 AFM研究表明,高质量的无孔薄膜的表面粗糙度很小,仅为6埃。通过XPS分析确认了Ti以四价态存在。通过电容-电压(C-V)和深能级瞬态光谱法(DLTS)研究了在Si / TiO2界面处观察到的缺陷参数。平带电压(V-FB)和慢速界面态的密度估计为-0.9,-0.44 V和5.24x10(10),1.03x10(11)cm(-2);分别用于NMOS和PMOS电容器。用DLTS测量的活化能,界面态密度和俘获截面为E-V + 0.30,E-C-0.21 eV;对于NMOS和PMOS结构,分别为8.73x10(11),6.41x10(11)eV(-1)cm(-2)和5.8x10(-23),8.11x10(-23)cm(2)。 P和N-MOS结构中的界面态密度值都很低,使其成为CMOS应用的合适替代介电层。而且由于缺陷的两性性质,两个载流子的俘获横截面的值都非常低,这表明陷阱不是积极的重组中心,可能在很大程度上无法促进器件的运行。 (C)2015年作者。

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