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Predicate abstraction and refinement techniques for verifying Verilog

机译:谓词抽象和优化技术,用于验证Verilog

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摘要

Abstract: \u22Model checking techniques applied to large industrial circuits suffer from the state explosion problem. A major technique to address this problem is abstraction. Predicate abstraction has been applied successfully to large software programs. Applying this technique to hardware designs poses additional challenges. This paper evaluates three techniques to improve the performance of SAT-based predicate abstraction of circuits: 1) We partition the abstraction problem by forming subsets of the predicates. The resulting abstractions are more coarse, but the computation of the abstract transition relation becomes easier. 2) We evaluate the performance effect of lazy abstraction, i.e., the abstraction is only performed if required by a spurious counterexample. 3) We use weakest preconditions of circuit transitions in order to obtain new predicates during refinement. We provide experimental results on publicly available benchmarks from the Texas97 benchmark suite.\u22
机译:摘要:用于大型工业电路的模型检查技术存在状态爆炸问题。解决此问题的主要技术是抽象。谓词抽象已成功应用于大型软件程序。将这种技术应用于硬件设计带来了其他挑战。本文评估了三种提高基于SAT的电路谓词抽象性能的技术:1)我们通过形成谓词的子集来划分抽象问题。生成的抽象更加粗糙,但是抽象过渡关系的计算变得更加容易。 2)我们评估延迟抽象的性能效果,即仅在虚假反例需要时才执行抽象。 3)我们使用电路转换的最弱前提条件,以便在优化过程中获得新的谓词。我们提供来自Texas97基准套件的公开基准的实验结果。\ u22

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