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Dynamic calibration of current-steering DAC

机译:电流控制DAC的动态校准

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摘要

The demand for high-speed communication systems has dramatically increased during the last decades. Working as an interface between the digital and analog world, Digital-to-Analog converters (DACs) are becoming more and more important because they are a key part which limits the accuracy and speed of an overall system. Consequently, the requirements for high-speed and high-accuracy DACs are increasingly demanding. It is well recognized that dynamic performance of the DACs degrades dramatically with increasing input signal frequencies and update rates. The dynamic performance is often characterized by the spurious free dynamic range (SFDR). The SFDR is determined by the spectral harmonics, which are attributable to system nonlinearities.;A new calibration approach is presented in this thesis that compensates for the dynamic errors in performance. In this approach, the nonlinear components of the input dependent and previous input code dependent errors are characterized, and correction codes that can be used to calibrate the DAC for these nonlinearities are stored in a two-dimensional error look-up table. A series of pulses is generated at run time by addressing the error look-up table with the most significant bits of the Boolean input and by using the corresponding output to drive a calibration DAC whose output is summed with the original DAC output. The approach is applied at both the behavioral level and the circuit level in current-steering DAC.;The validity of this approach is verified by simulation. These simulations show that the dynamic nonlinearities can be dramatically reduced with this calibration scheme. The simulation results also show that this calibration approach is robust to errors in both the width and height of calibration pulses.;Experimental measurement results are also provided for a special case of this dynamic calibration algorithm that show that the dynamic performance can be improved through dynamic calibration, provided the mean error values in the table are close to their real values.
机译:在过去的几十年中,对高速通信系统的需求急剧增加。作为数字和模拟世界之间的接口,数模转换器(DAC)变得越来越重要,因为它们是限制整个系统的准确性和速度的关键部分。因此,对高速和高精度DAC的要求越来越高。众所周知,DAC的动态性能会随着输入信号频率和更新速率的增加而急剧下降。动态性能通常以无杂散动态范围(SFDR)为特征。 SFDR由频谱谐波确定,而频谱谐波可归因于系统非线性。本论文提出了一种新的校准方法,该方法可以补偿性能中的动态误差。在这种方法中,表征了与输入有关的误差和先前与输入代码有关的误差的非线性成分,并且可用于校正这些非线性的DAC的校正码存储在二维误差查找表中。在运行时,通过使用布尔输入的最高有效位寻址错误查找表并使用相应的输出来驱动校准DAC来产生一系列脉冲,该校准DAC的输出与原始DAC输出相加。该方法在电流控制DAC的行为和电路两方面都得到了应用。通过仿真验证了该方法的有效性。这些仿真表明,使用该校准方案可以大大降低动态非线性。仿真结果还表明,该校准方法对校准脉冲的宽度和高度误差均具有鲁棒性。该动态校准算法的特殊情况还提供了实验测量结果,表明可以通过动态调整来改善动态性能。校准,前提是表中的平均误差值接近其实际值。

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    Su, Chao;

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  • 年度 2007
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  • 原文格式 PDF
  • 正文语种 en
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