首页> 外文OA文献 >A 3-DIMENSIONAL HIGH-THROUGHPUT ARCHITECTURE USING THROUGH-WAFER OPTICAL INTERCONNECT
【2h】

A 3-DIMENSIONAL HIGH-THROUGHPUT ARCHITECTURE USING THROUGH-WAFER OPTICAL INTERCONNECT

机译:通过晶片晶圆光学互连的三维高通量架构

摘要

This paper presents a three-dimensional, highly parallel, optically interconnected system to process high-throughput stream data such as images, The vertical optical interconnections are realized using integrated optoelectronic devices operating at wavelengths to which silicon is transparent. These through-wafer optical signals are used to vertically optically interconnect stacked silicon circuits, The thin film optoelectronic devices are bonded directly to the stacked layers of silicon circuitry to realize self-contained vertical optical interconnections. Each integrated circuit layer contains analog interface circuitry, namely, detector amplifier and emitter driver circuitry, and digital circuitry for the network and/or processor, all of which are fabricated using a standard silicon integrated circuit foundry, These silicon circuits are post processed to integrate the thin him optoelectronics using standard, low cost, high yield microfabrication techniques. The three-dimensionally integrated architectures described herein are a network and a processor. The network has been designed to meet off-chip I/O using a new offset cube topology coupled with naming and routing schemes, The performance of this network is comparable to that of a three-dimensional mesh, The processing architecture has been defined to minimize overhead for basic parallel operations, The system goal for this research is to develop an integrated processing node for high-throughput, low-memory applications
机译:本文提出了一种三维,高度并行的光学互连系统,用于处理诸如图像之类的高通量流数据。垂直光学互连是通过使用在硅透明的波长下工作的集成光电器件来实现的。这些晶片光信号用于垂直光学互连堆叠的硅电路。薄膜光电器件直接键合到硅电路堆叠的层,以实现独立的垂直光学互连。每个集成电路层都包含模拟接口电路,即检测器放大器和发射极驱动器电路,以及用于网络和/或处理器的数字电路,所有这些均使用标准的硅集成电路代工厂制造。这些硅电路经过后处理以集成使用标准,低成本,高产量的微细加工技术来制造薄型光电器件。本文描述的三维集成架构是网络和处理器。该网络使用新的偏移多维数据集拓扑结构以及命名和路由方案来满足片外I / O的要求,该网络的性能与三维网格相当,处理体系结构已定义为最小化基本并行操作的开销,此研究的系统目标是为高吞吐量,低内存应用程序开发集成处理节点

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号