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Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS

机译:0.35-μmCMOS的12.8 ENOB,1 kS / s流水线SAR ADC设计

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摘要

This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.
机译:本文介绍了一种15位,两级流水线逐次逼近寄存器模数转换器(ADC),适用于低功耗,经济高效的传感器读出电路。在第二级中,在残余放大器中采用大幅降低增益的方法,并结合适当的电容阵列DAC拓扑结构,简化了运算跨导放大器的设计,同时消除了过多的电容性负载和随之而来的功耗。对整个ADC进行了详细的功耗分析,以确定流水线每一级的位数。为第一级和第二级选择分段电容阵列DAC和基于衰减电容器的DAC分别可以显着降低功耗和面积。原型ADC采用低成本0.35-μmCMOS工艺制造,在1kS / s的采样频率下实现了78.9dB的峰值SNDR,对应于12.8位的有效位数(ENOB),并提供了157.6的FoM D b。在不进行任何形式的校准的情况下,ADC的ENOB> 12.1位高达500Hz的奈奎斯特带宽,而功耗为6.7μW。 ADC的核心面积为0.679 mm2。

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