Diseño de módulo Serializador de un sistema SerDes para protocolo de comunicación PCI Express

摘要

This document presents the process followed for designing of a VLSI circuit, specifically the Serializer module of a SerDes used in the PCI Express protocol communication. It is shown a proposed architecture, the implementation of a RTL model in Verilog, the logic synthesis, the physical synthesis and the generation of a GDSII file for manufacturing. The Serializer of a SerDes for PCIe obtains a parallel 8 bits datum and returns a serialized 10 bit encoded datum using 8b/10b encoding. The technology used for this project is the cmrf_7sf from IBM.