Diseño de circuito analógico de polarización para sistema SerDes

摘要

In this report the design and development stage of the polarization of an analog receiver for a SerDes system is presented. The stage consists of an OTA and a BIAS current circuit. The results of pre-layout validation and validation results of post-layout will be presented.The circuit design is based on IBM 180 nm CMOS technology. The first stage envisages the validation of results without the integration of the power amplifier module; it includes only the results according to the design specifications achieving the expected result for both, the bandwidth and the gain in dB of the stage. The second stage includes improvements to the final design eliminating the test circuits (voltage sources) including the integration of the amplification stage for the analog receiver circuit. For the second stage the main objective is to show the process for mismatch validation test, in addition the validation process for closed loop sample, which will be shown in the OTA circuit, for post-layout design will be validated through DRC and LVS test.