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Design and characterization of interposers for high speed fine pitch wafer level packaged device testing

机译：高速细间距晶圆级封装器件测试用中介层的设计与表征

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TAN PANG HOAW JIMMY;
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年度 2006
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1. Design and Demonstration of Fine-Pitch and High-Speed Redistribution Layers for Panel-Based Glass Interposers at 40-μm Bump Pitch [J] . Brett Sawyer, Yuya Suzuki, Zihan Wu, Journal of Microelectronics and Electronic Packaging . 2016,第3期

机译：用于40微米凸块间距的基于面板的玻璃插入器的细间距和高速再分配层的设计与演示
2. Design and Development of Fine Pitch Copper/Low-K Wafer Level Package [J] . Advanced Packaging, IEEE Transactions on . 2010,第2期

机译：细间距铜/低K晶圆级封装的设计与开发
3. Fabrication and characterization of fine pitch on-chip copper interconnects for advanced wafer level packaging by a high aspect ratio through AZ9260 resist electroplating [J] . Pradeep Dixit, Chee Wee Tan, Luhua Xu, Journal of Micromechanics and Microengineering . 2007,第5期

机译：通过AZ9260抗蚀剂电镀以高深宽比制造和表征用于高级晶圆级封装的细间距片上铜互连
4. Test bench modeling and characterization for fine pitch wafer level packaged devices [C] . Jayabalan J., Mihai R.D., Tan J.P.H., Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th . 2004

机译：细间距晶圆级封装设备的测试台建模和表征
5. Design, fabrication and testing of conformal, localized wafer-level packaging for RF MEMS devices. [D] . Collins, Gustina B. 2006

机译：设计，制造和测试用于RF MEMS器件的保形，局部晶圆级封装。
6. Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer [O] . Azrul Azlan Hamzah, Jumril Yunas, Burhanuddin Yeop Majlis, 2008

机译：溅射封装作为可隔离MEMS器件的晶圆级封装：电容式加速度计上展示的一项技术
7. Simulation and fabrication of an interposer for electrical testing of fine-pitch wafer-level packages [O] . DENG CHUN 2004

机译：用于细间距晶圆级封装的电气测试的中介层的仿真和制造

Design and characterization of interposers for high speed fine pitch wafer level packaged device testing

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