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Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package

机译：PEEC建模在开发具有细间距晶圆级封装的新型多千兆赫测试接口中的应用

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JAYASANKER JAYABALAN;
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年度 2006
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2. Design and Development of Fine Pitch Copper/Low-K Wafer Level Package [J] . Advanced Packaging, IEEE Transactions on . 2010 ,第2期

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7. Design and characterization of interposers for high speed fine pitch wafer level packaged device testing [O] . TAN PANG HOAW JIMMY 2006

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Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package

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