CMOS design enhancement techniques for RF receivers. Analysis, design and implementation of RF receivers with component enhancement and component reduction for improved sensitivity and reduced cost, using CMOS technology.

摘要

Silicon CMOS Technology is now the preferred process for low power wirelessudcommunication devices, although currently much noisier and slower than comparableudprocesses such as SiGe Bipolar and GaAs technologies. However, due to ever-reducingudgate sizes and correspondingly higher speeds, higher Ft CMOS processes areudincreasingly competitive, especially in low power wireless systems such as Bluetooth,udWireless USB, Wimax, Zigbee and W-CDMA transceivers. With the current 32 nm gateudsized devices, speeds of 100 GHz and beyond are well within the horizon for CMOSudtechnology, but at a reduced operational voltage, even with thicker gate oxides asudcompensation.udThis thesis investigates newer techniques, both from a systems point of view and at audcircuit level, to implement an efficient transceiver design that will produce a moreudsensitive receiver, overcoming the noise disadvantage of using CMOS Silicon. As audstarting point, the overall components and available SoC were investigated, togetherudwith their architecture.udTwo novel techniques were developed during this investigation. The first was a highudcompression point LNA design giving a lower overall systems noise figure for theudreceiver. The second was an innovative means of matching circuits with low Qudcomponents, which enabled the use of smaller inductors and reduced the attenuationudloss of the components, the resulting smaller circuit die size leading to smaller andudlower cost commercial radio equipment. Both these techniques have had patents filed by theudUniversity.udFinally, the overall design was laid out for fabrication, taking into account packageudconstraints and bond-wire effects and other parasitic EMC effects.