Power and Noise Configurable Phase-Locked Loop Using Multi-Oscillator Feedback Alignment

摘要

On-the-fly data rate changes allow for the data rate to be lowered when peak speeds are not needed. A PLL is presented that contains a plurality of sub-VCOs, each able to be enabled or disabled. The goal of this technique is having the power dissipation proportional to the data rate, in order to obtain a fixed energy per transmitted bit. The proposed architecture accomplishes data rate changes by quickly reconfiguring itself and exploiting known power / jitter trade offs in circuit design. The proposed architecture can be applied to either electrical or optical serial links that do not contain a forwarded clock.ududBy relaxing the jitter constraints at lower data rates, the receiver can enter a low-power mode enabling energy savings when maximum data rates are not required. A bank of sub-VCOs is introduced and can be brought up to speed and connected. An activation procedure and compensation methods have also been introduced in order to avoid arbitrary phases during start-up, which would lead to large phase excursions. Simulations show that by enabling the high-performance mode, data rates of 25 Gb/s are able to be obtained in a CDR setting. In the low power mode, the jitter increases by 1.5 times but the power reduces by 46%. In this mode, the architecture can support data rates of 12.5 Gb/s. Therefore, this system responds to the need of improving energy efficiency in receivers by allowing a dynamic reconfiguration of the circuit; varying power in response to jitter specifications.ud