Structure design challenge in nano-cmos device.

摘要

This paper intends to report the problems andchallenges that lie ahead in transistor designmethodology in nano-CMOS structure. Thus, it isdesired to see the options in improving the devicedesign on top of continuing the scaling process oftransistor in the next few years to come. The mainconcern is to see how the transistors behave as thesize of device shrinks down to below 100nm range.Besides, the demand of future generations isexpected as a result of more compact of digitalcircuit. It is concluded that although severalproblems surfaces as the transistor enters the nano-CMOS era, there are excellent options to solve thoseproblems and thus could help to reduce thetransistor size and yet uncompromised the deviceperformance.