Standard cell library tuning for variability tolerant designs

摘要

In todayu26apos;s semiconductor industry we see a move towards smaller technology feature sizes. These smaller feature sizes pose a problem in terms of process controllability, e.g. mismatch between identical cells on a single die known as local variation. In this paper a library tuning method is proposed which makes a smart selection of cells in a standard cell library to reduce the designu26apos;s sensitivity to local variability. This results in a robust IC design with an identifiable behavior towards local variations. Experimental results performed on a widely used microprocessor design synthesized for a high performance timing show that we can achieve a timing spread reduction of 37% at an area increase cost of 7%. In todayu26apos;s semiconductor industry we see a move towards smaller technology feature sizes. These smaller feature sizes pose a problem in terms of process controllability, e.g. mismatch between identical cells on a single die known as local variation. In this paper a library tuning method is proposed which makes a smart selection of cells in a standard cell library to reduce the designu26apos;s sensitivity to local variability. This results in a robust IC design with an identifiable behavior towards local variations. Experimental results performed on a widely used microprocessor design synthesized for a high performance timing show that we can achieve a timing spread reduction of 37% at an area increase cost of 7%.