Projeto e prototipação de interfaces e redes intrachip não-síncronas em FGPAs

摘要

The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip. However, this evolution is rendering less viable some well-established design practices. Examples of these are the use of multipoint communication architectures (e. g. busses) and designing fully synchronous systems. In addition, power dissipation is becoming one of the main design concerns due e. g. to the increasing use of mobile products such as PDAs, mobile phones and laptop computers. An alternative to overcome the design practices becoming unviable is adopting Networks on Chip (NoCs) communication architectures supporting globally asynchronous locally synchronous (GALS) system design. This work has as main goal the development of features to support the design of GALS systems in FPGAs devices. The selection of FPGAs as target architecture occurred because several of these commercial devices already contain features supporting the design of GALS systems, such as the availability of multiple independent clock domains. Also, FPGAs are used in many scenarios as an important verification step in the design of complex integrated circuits. This works explores three development axes for enabling GALS design in FPGAs. Each one led to its own set of usable, practical results. First, there is the proposition and design of a macro block library of asynchronous devices for FPGAs. The cells of this library can be used to create compact and efficient non-synchronous modules in FPGAs. Second, after comparing a set of approaches for developing asynchronous interfaces in FPGAs and ASICS, the SCAFFI family of asynchronous interfaces was proposed. SCAFFI allows that modules operating in distinct clock domains interconnect to each other seamlessly. Third, two NoC routers supporting the GALS systems were proposed and validated: Hermes GALS (Hermes-G) and Hermes GALS Low Power (Hermes-GLP). The Hermes-GLP router, besides supporting the development of GALS systems, takes advantage of the GALS design style to reduce power dissipation in the routers. The way to achieve this is to add frequency switching mechanisms to the latter. Some circuits have been employed as case studies to validate the two first development axes, including an RSA cryptography core and combinational and pipeline multipliers. The most relevant strategic contribution of this work is the generation of a basic infrastructure for the design of GALS systems in FPGAs.