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Monitoramento do fluxo de controle de processadores embarcados baseado em profiling de software

机译:基于软件配置文件的嵌入式处理器的控制流监视

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摘要

In the recent years, the society observes with enthusiasm the rapid proliferation of a vast diversity of embedded systems targeted to safe-critical applications like health-care systems, telecommunication, automotive and aerospace. As a consequence, besides the need for low-cost components, mainly memory, it is also mandatory the use of more robustness hardware and software parts that integrate these systems. Among the possible types of faults, those that change the control-flow of the processors that carry out embedded applications are focused on this work. Very often, these types of faults induce in catastrophic system failure. By catastrophic failure, we mean those faults that in addition to drive the system to an unexpected behavior, it is also needed to reinitialize the system to recover from the faulty state. Thus, the use of techniques capable of detecting these types of faults prevents them from spreading through the system and ultimately, generating incorrect outputs. Unfortunately, the use of fault detection techniques increase memory overhead and degrades system performance. These collateral effects may be critical, preventing real-time embedded systems from attaining their goals. As possible solutions to the mentioned problems, three hypotheses were investigated, and one of them was implemented. Therefore, this work proposes an approach based on software profiling that analyses the control-flow graph of applications, to optimize the number of checkpoints to be inserted along with the application code. In order to validate the proposed approach, we performed fault injection of three types of faults: jump, nop and bit-flips. This fault injection process was accelerated by means of hardware prototyping of the system. In this case, we used a FPGA (Field-Programmable Gate Array) mounted on a Xilinx commercial board. Detailed analysis of the obtained results indicates that the proposed approach reduces the number of checkpoints to be inserted along with the application code, thus, minimizing memory overhead and system performance degradation, while maintaining approximately unchanged the fault detection coverage, when compared to another existing approaches in the literature.
机译:近年来,社会热情地观察到针对安全关键型应用(如医疗保健系统,电信,汽车和航空航天)的各种嵌入式系统的迅速扩散。因此,除了需要低成本组件(主要是内存)外,还必须使用集成这些系统的更强大的硬件和软件部件。在可能的故障类型中,那些会改变执行嵌入式应用程序的处理器的控制流的故障集中在这项工作上。通常,这些类型的故障会导致灾难性的系统故障。灾难性故障是指那些不仅导致系统异常运行的故障,还需要重新初始化系统以从故障状态中恢复。因此,使用能够检测这些类型的故障的技术可防止它们在系统中传播,并最终产生不正确的输出。不幸的是,使用故障检测技术会增加内存开销并降低系统性能。这些附带影响可能很关键,从而阻碍了实时嵌入式系统实现其目标。作为解决上述问题的可能方法,研究了三个假设,并实施了其中一个假设。因此,这项工作提出了一种基于软件性能分析的方法,该方法分析了应用程序的控制流图,以优化与应用程序代码一起插入的检查点的数量。为了验证所提出的方法,我们对三种类型的故障进行了故障注入:跳跃,nop和位翻转。通过系统的硬件原型设计加快了故障注入过程。在这种情况下,我们使用了安装在Xilinx商业板上的FPGA(现场可编程门阵列)。对获得的结果的详细分析表明,与其他现有方法相比,所提出的方法减少了与应用程序代码一起插入的检查点的数量,从而最大程度地减少了内存开销和系统性能下降,同时保持了几乎不变的故障检测范围。在文学中。

著录项

  • 作者

    Rocha Cláudia Antunes;

  • 作者单位
  • 年度 2007
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  • 原文格式 PDF
  • 正文语种 Português
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