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Design and implementing Asynchronous Circuit based on Quasi Delay Insensitive model

机译：基于准时滞不敏感模型的异步电路设计与实现

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博士（工学）

机译：博士（工学）

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仲程基経; Nakahodo Motosune;
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年度 2015
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正文语种 jpn
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专利

1. A Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous Circuits [J] . D. Jayanthi, M. Rajaram Journal of computer sciences . 2012,第7期

机译：使用流水线模板的异步电路的准延迟不敏感的减少堆栈预充电半缓冲区高速加法器
2. A Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous Circuits | Science Publications [J] . D. Jayanthi, M. Rajaram Journal of computer sciences . 2012,第7期

机译：准延迟不敏感的减少堆栈预充电半缓冲区的高速加法器，使用异步电路的流水线模板科学出版物
3. An Efficient Energy Estimation Methodology for Quasi Delay Insensitive Template-Based Asynchronous Circuits [J] . Behnam Ghavami, Hossein Pedram, Mahtab Niknahad Journal of Low Power Electronics . 2010,第1期

机译：基于准延迟不敏感模板的异步电路的高效能量估计方法
4. Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits [C] . Yi-Fan Evan Chang, Ruei-Yang Huang, Jie-Hong R. Jiang IEEE International Symposium on Asynchronous Circuits and Systems . 2019

机译：有效利用FPGA资源来实现异步电路的准延迟不敏感实现
5. Formal Modeling and Verification Methodologies for Quasi-Delay Insensitive Asynchronous Circuits [D] . Sakib, Ashiq Adnan. 2019

机译：准延迟不敏感异步电路的正式建模与验证方法
6. Asynchronous quasi delay insensitive majority voters corresponding to quintuple modular redundancy for mission/safety-critical applications [O] . P. Balasubramanian, N. E. Mastorakis 2020

机译：异步准延迟不敏感的多数选民对应于Quintuple模块化冗余的任务/安全关键应用程序
7. A Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous Circuits [O] . M. Rajaram, D. Jayanthi 2012

机译：使用流水线模板的异步电路的准延迟不敏感的减少堆栈预充电半缓冲区高速加法器
8. Limitations to Delay-Insensitivity in Asynchronous Circuits. [R] . Martin, A. J. 1990

机译：异步电路中延迟不敏感的局限性。

Design and implementing Asynchronous Circuit based on Quasi Delay Insensitive model

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