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Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation

机译:使用积极的扩展功能和时序推测功能实现高能效和抗功率攻击的系统设计和分析

摘要

Growing usage of smart and portable electronic devices demands embedded system designers to provide solutions with better performance and reduced power consumption. Due to the new development of IoT and embedded systems usage, not only power and performance of these devices but also security of them is becoming an important design constraint. In this work, a novel aggressive scaling based on timing speculation is proposed to overcome the drawbacks of traditional DVFS and provide security from power analysis attacks at the same time. udDynamic voltage and frequency scaling (DVFS) is proven to be the most suitable technique for power efficiency in processor designs. Due to its promising benefits, the technique is still getting researchers attention to trade off power and performance of modern processor designs. The issues of traditional DVFS are: 1) Due to its pre-calculated operating points, the system is not able to suit to modern process variations. 2) Since Process Voltage and Temperature (PVT) variations are not considered, large timing margins are added to guarantee a safe operation in the presence of variations.udThe research work presented here addresses these issues by employing aggressive scaling mechanisms to achieve more power savings with increased performance. This approach uses in-situ timing error monitoring and recovering mechanisms to reduce extra timing margins and to account for process variations. A novel timing error detection and correction mechanism, to achieve more power savings or high performance, is presented. This novel technique has also been shown to improve security of processors against differential power analysis attacks technique. Differential power analysis attacks can extract secret information from embedded systems without knowing much details about the internal architecture of the device. Simulated and experimental data show that the novel technique can provide a performance improvement of 24% or power savings of 44% while occupying less area and power overhead. Overall, the proposed aggressive scaling technique provides an improvement in power consumption and performance while increasing the security of processors from power analysis attacks.
机译:智能和便携式电子设备的使用不断增长,要求嵌入式系统设计人员提供具有更好性能和降低功耗的解决方案。由于物联网和嵌入式系统使用的新发展,不仅这些设备的功率和性能,而且它们的安全性也成为重要的设计约束。在这项工作中,提出了一种基于时序推测的新颖主动缩放,以克服传统DVFS的缺点,并同时提供针对功耗分析攻击的安全性。动态电压和频率缩放(DVFS)被证明是处理器设计中提高功率效率的最合适技术。由于其前景广阔的前景,该技术仍在吸引研究人员注意权衡现代处理器设计的功能和性能。传统DVFS的问题是:1)由于其预先计算的工作点,该系统无法适应现代工艺的变化。 2)由于不考虑工艺电压和温度(PVT)的变化,因此添加了较大的时序裕度,以确保在存在变化的情况下安全运行。 ud本文介绍的研究工作通过采用积极的缩放机制来解决这些问题,以实现更多的节能效果提高性能。这种方法使用原位定时误差监视和恢复机制来减少额外的定时余量并解决工艺变化。提出了一种新颖的定时错误检测和校正机制,以实现更多的节能或高性能。还已经显示出这种新颖技术可以提高处理器抵抗差分功率分析攻击技术的安全性。差分功率分析攻击可以从嵌入式系统中提取秘密信息,而无需了解有关设备内部架构的详细信息。仿真和实验数据表明,该新技术可以提供24%的性能提升或44%的功耗节省,同时占用更少的面积和功耗。总体而言,所提出的积极的扩展技术可改善功耗和性能,同时提高处理器免受功耗分析攻击的安全性。

著录项

  • 作者

    Rathnala Prasanthi;

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  • 年度 2017
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  • 原文格式 PDF
  • 正文语种 en
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