Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filters

摘要

A simple and robust circuit for the input commonmode voltage generation in CMOS pseudo-differential inverter-based transconductors is proposed. The solution can improve the in-band IIP3 in 7.8dBVp and the 1-dB compression point in 5.3dBVp compared to conventional approaches, with less noise, power consumption and occupied die area. A 1.2V 3.42mW 1.3-3.7MHz high-linear 8th order bandpass complex filter is presented as demonstrator in a CMOS 90nm process. The yield for an image rejection ration IRR above 50dB is 86%, which represents a 31% improvement respect to the classical approach.