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High speed time-multiplexed continuous time Sigma-Delta converters

机译:高速时分多路连续时间Sigma-Delta转换器

摘要

This paper presents a time-interleaved continuous time Sigma-Delta converter, which uses 4 identical channels clocked at equally shifted time moments of a 4 GHz clock.The data in each channel is filtered and afterwards recombined in a multiplexer, leading to an output signal at 4 GHz before decimation. Time-interleaving as proposed in this paper makes it possible to increase the signal-to-noise and distortion ratio (SNDR) in a specified bandwidth with 3 dB every time the number of channels is doubled. By exchanging the gain in accuracy for bandwidth, a high-speed Sigma-Delta converter with 250 MHz signal bandwidth and 65 dB SNDR is obtained in simulations. The simulated converter achieves a dynamic range of 72 dB and consumes 626 mW, leading to a Schreier FOM of 158 dB and a Walden FOM of 864.5 fJ/conv. This paper briefly discusses the different building blocks of the interleaved converter and their influence on the performance.
机译:本文介绍了一种时间交错的连续时间Sigma-Delta转换器,该转换器使用4个相同的通道,分别以4 GHz时钟的相同偏移时间进行计时,每个通道中的数据经过滤波后在多路复用器中重组,从而产生输出信号抽取前在4 GHz下本文提出的时间交织使得每增加一倍的信道数量,就可以在指定带宽内以3 dB的幅度增加信噪比和失真比(SNDR)。通过交换带宽精度的增益,可以在仿真中获得具有250 MHz信号带宽和65 dB SNDR的高速Sigma-Delta转换器。模拟转换器实现72 dB的动态范围,消耗626 mW,从而产生158 dB的Schreier FOM和864.5 fJ / conv的Walden FOM。本文简要讨论了交错转换器的不同构建模块及其对性能的影响。

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  • 作者

    De Pelecijn Elly;

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  • 年度 2017
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